1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor substrate. More specifically, it relates to a technique that involves heat-treating a single-crystal wafer in which light element has been ion-implanted at a predetermined depth position, then splitting off the single-crystal wafer from inside the ion-implanted region.
2. Background Art
Recently developed methods for manufacturing semiconductor wafers having a silicon-on-insulator (SOI) structure include the Smart Cut process described in Japanese Patent Application, First Publication No. H05-211128.
The Smart Cut process begins by ion-implanting hydrogen (a light element) to a predetermined depth position in an active-layer-forming wafer, then bonding together the ion-implanted active-layer-forming wafer and a supporting wafer for supporting the active-layer-forming wafer, with an oxide layer therebetween, to form a bonded wafer. The bonded wafer is then placed in a heat treatment furnace and subjected to bonding heat treatment, during which hydrogen bubbles form within the ion-implanted region. Hydrogen bubble formation causes the active-layer-forming wafer to split off, leaving behind an active layer, over the intervening oxide layer, on the supporting wafer side, thereby giving a bonded SOI wafer.
In the prior art, a (100) wafer composed of single-crystal silicon whose surface is a (100) plane is used as the active-layer-forming wafer. Moreover, during this heat treatment, the entire region within the wafer plane is heated at substantially the same time to a temperature greater than the hydrogen bubble forming temperature.
Prior-art active-layer-forming wafers are (100) wafers in which the wafer surface is a (100) plane. But, because the (100) plane is not a cleavage plane, the hydrogen bubbles form irregularly throughout the thickness direction in the ion-implanted region during heat treatment. Hence, the split surface of the active layer has a large roughness, increasing the amount of polishing in the polishing step, or etching in the etching step, required to planarize the wafer after splitting. The result has been a lower in-plane uniformity in the thickness of the active layer, preventing a high flatness from being achieved.